With the advent of the computer age, electronic systems have become a staple of modern life, and some may even deem them a necessity. Part and parcel with this spread of technology comes an ever greater drive for more functionality from these electronic systems. A microcosm of this quest for increased functionality is the size and capacity of various semiconductor devices. From the 8 bit microprocessor of the original Apple I, through the 16 bit processors of the original IBM PC AT, to the current day, the processing power of semiconductors has grown while the size of these semiconductors has consistently been reduce. In fact, Moore's law recites that the number of transistors on a given size piece of silicon will double every 18 months.
As semiconductors have evolved into these complex systems utilized in powerful computing architectures, almost universally, the connectivity and power requirements for these semiconductors have been increasing. These increased connectivity requirements have meant that the number of pins on semiconductors is steadily increasing as well. These high pin counts have ramifications on the semiconductor packages used in conjunction with these semiconductors.
One type of semiconductor package utilized in conjunction with a semiconductor is a wire bonding type package. In this type of semiconductor package, it is usually the case that bonding pads on the semiconductor die can be arranged only along the edges of the die. Therefore, in a wire bonding type package the maximum pin count of a semiconductor device may be restricted by the size of the die of the semiconductor.
Another type of semiconductor package, which may be more suitable for high pin count devices, is a flip chip package. Turning briefly to FIG. 1, one embodiment of a flip chip semiconductor package is depicted. Die 110 containing a semiconductor, such as a microprocessor, is attached to substrate 120. Die 110 may have an array of bonding pads coupled to a corresponding array of C4 pads on substrate 120. Each of these C4 pads may be coupled to a ball grid array (BGA) bonding pad on substrate 120 through a signal trace. These BGA bonding pads are in turn coupled to substrate BGA balls 130 which serve to couple die 110 to a power source or signal input/output lines. Typically substrate 120, with which microprocessors or semiconductors are packaged, is made of organic material (such as epoxy resin) and may be fabricated using build-up technology, which enables higher wiring capability by having fine-line build-up layer(s) on both sides of a coarser core substrate. As bonding pads may be arranged in an array on die 110, flip chip package 100 may be more suitable for use with a semiconductor having a high pin count.
In main, there are two ways to achieve signaling in a semiconductor package, single ended signaling and differential signaling. In single ended signaling a single trace may be used in conjunction with a positive voltage and a reference voltage (usually ground). As the reference voltage may vary over distance differential signaling may be a superior methodology for some applications. Differential signaling uses two signal traces for each signal for immunity to noise and crosstalk. In differential signaling a signal is sent down one wire as positive and the other as negative, and the circuit at the receiving end derives the signal from the difference between the two.
Turning to FIG. 2, one embodiment of signal routing on a portion of a package substrate of a semiconductor package which employs differential signaling is illustrated. C4 pads 210 on substrate 200 are connected to one BGA pad 220 using signal traces 212. Each pair 214 of signal traces 212 is utilized to carry one signal to or from C4 pads 210 which are coupled to a semiconductor die (not shown). This semiconductor can then derive the signal from the difference between the pair of signal traces 214.
No matter the type of signaling used in a semiconductor package, however, it is important to signal integrity that impedance is substantially matched in an entire signal trace. This may be especially true in the case of high-speed signals. The impedance of a signal trace is, however, affected by the density of the signal traces in a package. More specifically, a coupling effect between adjacent signal traces in close proximity to one another may serve to decrease the impedance of a signal trace. As C4 bumps for the coupling of a semiconductor die are usually much closer to one another than the BGA pads on a substrate, crowding of signal traces frequently occurs in semiconductor packages in a region proximal to the C4 pads.
Referring again to FIG. 2, suppose each signal trace has an impedance of 100 ohms and that in high signal density region 240, proximal to C4 pads 210, the distance between each signal trace 212 in a pair of signal traces 214 may be substantially equal to the distance between adjacent signal trace pairs 214. Usually in high signal density region 240 the distance between adjacent signal pairs 214 is less than 200 microns. This may lead to a decrease of around 3 ohms in the impedance of signal traces 212 in region 240.
Typically, to solve this problem use narrower trace widths in a high signal density region. This solution, however, increases the cost of manufacturing the package substrate of a semiconductor package while simultaneously reducing the manufacturing yields of this substrate. Additionally, the impedance tolerance may increase with these narrower trace widths.
Another solution to this problem is to use a thicker dielectric material to form the substrate in the high signal density region and wider trace width in the area outside of the high signal density region. This solution may make it more difficult to form vias in the substrate, and may be an additional obstacle to fine pitch substrate.
Yet another solution to this problem is to increase the number of routing layers in the package substrate. This solution, however, may be prohibitively expensive to implement.
Thus, a need exists for a semiconductor package with improved impedance matching in signal traces within the semiconductor package.